1. Field of the Invention
The invention relates generally to semiconductor devices, and more particularly, to a semiconductor device and the operating method thereof, containing a voltage converting circuit for converting an externally applied power supply voltage to a predetermined voltage and providing the same to an internal circuit.
2. Description of the Background Art
Recently, examples of development have been published in a 4M-bit static random access memory (hereinafter referred to as SRAM) and a 16M-bit dynamic random access memory (hereinafter referred to as DRAM) utilizing a micro-lithography technology at a 0.5 .mu.m level. In these 4M-bit SRAM and 16M-bit DRAM, a short channel MOS transistor is used, having a gate length of 0.6 .mu.m or below. In a conventional 4M-bit DRAM and the like, an MOS transistor is used, which has a gate length from 1 .mu.m to about 0.8 .mu.m, and operates at a power supply voltage of 5 V.
When a short channel MOS transistor, which is used in the above-mentioned 4M-bit SRAM and 16M-bit DRAM, is operated at a power supply voltage of 5 V, it is noted that a degradation of a transistor characteristic is caused to a degree that is not negligible, presenting a problem of reliability.
In order to use a short channel MOS transistor having a gate length of about 0.5 .mu.m, controlling such a degradation of the transistor characteristic, it is intended to change the power supply voltage from 5 V, for example, to 3.3 V. When a compatibility with a power supply system of 5 V which has been widely used so far is considered, however, there is a problem in the change of a power supply voltage.
Accordingly, a semiconductor device is proposed, in which a voltage converting circuit is integrated. In the semiconductor device, an externally applied power supply voltage is held at 5 V, and the power supply voltage is reduced to a constant voltage by the voltage converting circuit, thereby allowing the internal circuit to be operated at a constant voltage independent of the fluctuation of the power supply voltage.
FIG. 14 is a block diagram showing one example of a conventional semiconductor device containing a voltage converting circuit. FIG. 15 is a diagram showing a specified circuit structure of the voltage converting circuit shown in FIG. 14. The voltage converting circuit of FIG. 15 is proposed, for example, by T. Furuyama et al. in IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, pp. 437-441, June 1987.
The semiconductor device 100 of FIG. 14 contains a voltage converting circuit 101, an internal circuit 105 and an input-output circuit 106. The internal circuit 105 comprises a memory, for example, a DRAM.
The voltage converting circuit 101 contains a reference voltage generating circuit 102, a differential amplifier 103 and a switching circuit 104. The semiconductor device 100 has a power supply terminal 10 for receiving a power supply voltage Vcc and a ground terminal 30 for receiving a ground voltage Vss. The reference voltage generating circuit 102 receives the externally applied power supply voltage Vcc and generates a reference voltage Vr almost independent of the power supply voltage Vcc. The reference voltage Vr is supplied to the differential amplifier 103, and an internal voltage Vi independent of the fluctuations of the power supply voltage Vcc and the load current is generated by the differential amplifier 103 and the switching circuit 104 and supplied to the internal circuit 105. The power supply voltage Vcc is, for example, 5 V, and the internal voltage Vi is, for example, 3.5 V.
The input-output circuit 106 is often directly driven by the power supply voltage Vcc externally applied, taking account of the connection with the peripheral logic LSI of a 5 V power supply system. Therefore, it is planned not to use a minimum gate length in the transistor of the input-output circuit 106. When the internal circuit 105 contains a memory such as a DRAM, the input-output circuit 106 mainly contains a buffer circuit. The input-output circuit 106 externally receives an address signal AD over an address terminal 40, and supplies the address signal AD to the internal circuit 105. The input-output circuit 106 supplies data DQ read from the internal circuit 105 to an external circuit over a data terminal 50, or provides externally applied DQ to the data terminal 50 to the internal circuit 105. Furthermore, the input-output circuit 106 provides a control signal CNT externally applied over a control terminal 60 to the internal circuit 105.
In FIG. 15, the reference voltage generating circuit 102 contains P channel MOS transistors 21 to 25. The transistors 21 to 23 are serially connected between the power supply terminal 10 and the ground terminal 30. The power supply voltage Vcc is voltage-divided by the transistors 21 to 23, and the voltage-divided voltage appears on the node N1. The transistor 24 is connected between the power supply terminal 10 and the node N2, and the transistor 25 is connected between the node N2 and the ground terminal 30.
When the power supply voltage Vcc is increased, the voltage of the node N1 is also increased, causing the transistor 24 to be in a non-conductive state. Thus, the increase in the voltage of the node N2 is prevented. Conversely, when the power supply voltage Vcc is reduced, the voltage of the node N1 is also reduced, causing the transistor 24 to be in a conductive state. Thus, the reduction in the voltage of the node N2 is prevented. In this way, a reference voltage Vr is generated from the node N2, almost independent of the fluctuation of the power supply voltage Vcc.
The differential amplifier 103 contains a current mirror circuit including P channel MOS transistors 31, 32 and N channel MOS transistors 33, 34. The gate of the transistor 31 is connected to the node N2 of the reference voltage generating circuit 102. A large-sized P channel MOS transistor 35 and a small-sized P channel MOS transistor 36 are connected between the node N3 which is a connection point of the transistors 31 and 32, and the power supply terminal 10. These transistors 35, 36 are added for reducing power consumption of the current mirror circuit.
In the period in which the internal circuit 105 operates, a clock signal .phi.0 applied to the gate of the transistor 35 attains a low level (logically low level), and the transistor 35 turns on. Thus, the responsibility of the current mirror circuit is increased. In the period in which the internal circuit 105 does not operate, the clock signal .phi.0 attains a high level (logically high level), and the transistor 35 turns off. In this case, the small-sized transistor 36 where a very small amount of current flows only turns on, so that the power consumption is controlled.
The switching circuit 104 includes a P channel MOS transistor 41. The gate of the transistor 32 in the current mirror circuit is connected to the node N4. The transistor 41 is connected between the power supply terminal 10 and the node N4. The gate of the transistor 41 is connected to the node N5 which is a connection point of the transistor 31 and the transistor 33 in the current mirror circuit.
When the internal voltage Vi supplied from the node N4 becomes higher than the reference voltage Vr, the value of the current flowing through the transistor 31 becomes larger than the value of the current flowing through the transistor 32. Thus the potential of the node N5 is increased. The transistor 41, therefore, falls in a weakly conductive state or a non-conductive state. As a result, the provision of the current from the power supply terminal 10 to the node N4 is stopped or reduced, and the internal voltage Vi is decreased.
Conversely, when the internal voltage Vi becomes lower than the reference voltage Vr, the value of the current flowing through the transistor 31 becomes smaller than the value of the current flowing through the transistor 32. The potential of the node N5 is decreased. Therefore, the transistor 41 falls in a conductive state, and a sufficient amount of current is supplied from the power supply terminal 10 to the node N4. As a result, the internal voltage Vi is increased.
Thus, a constant internal voltage Vi may be obtained, independent of the fluctuation of the power supply voltage Vcc or the fluctuation of the load current.
FIG. 16 is a diagram showing a voltage converting characteristic of the voltage converting circuit in FIG. 15. In FIG. 16, the marks O indicate measured values, and the solid line L1 shows a simulated characteristic.
As shown in FIG. 16, the internal voltage Vi is kept at about 3.5 V set as the reference voltage Vr in the region where the externally applied power supply voltage Vcc is about 3.5 V or above.
In order to assure a stable operation of semiconductor devices used in a variety of environments, devices whose operations are unstable are rejected as defective, effecting an operating margin test before shipping. In the operating margin test, an operating test of a semiconductor device is conducted, providing a low voltage or a high voltage exceeding the range of operation ensuring voltage to the semiconductor. When 5 V.+-.10% of operation is to be assured, for example, the test is conducted within the range of 5 V.+-.20%.
In order to effect screening of defective products at the time of shipping, or assume the lifetime when used for long time, an acceleration aging test is effected by externally applying a high voltage as would not be normally used as a power supply voltage Vcc to the semiconductor device. For example, when the normal power supply voltage Vcc is 5 V, a high voltage of 7 V is applied. In this case, screening of defective products means selecting defective products by an acceleration aging test in order to insure the reliability of the semiconductor device in the market. When such an operating margin test and an acceleration aging test are intended to be applied to a semiconductor device containing a voltage converting circuit as shown in FIG. 14, as will be apparent from FIG. 16, the externally applied high voltage is not applied in the chip, so that an effective test can not be conducted.
FIG. 17 shows a semiconductor integrated circuit device capable of externally applying a high voltage in an acceleration aging test. The semiconductor integrated circuit device in FIG. 17 is disclosed in Japanese Patent Laying-Open No. 64-55857.
In FIG. 17, a power supply voltage converting circuit 111 externally receives the power supply voltage Vcc and generates an internal voltage Vi at a lower level than that of the power supply voltage Vcc. Normally, the internal voltage Vi generated from the power supply voltage generating circuit 111 is provided to an integrated circuit block 113 over an internal power supply line 112. In an acceleration aging test, a transistor 114 attains a conductive stage by a switching signal .phi.1, and an externally applied high voltage Ve is supplied to the integrated circuit block 113 over the transistor 114 and the internal power supply line 112.
In the semiconductor integrated circuit device of FIG. 17, a variety of tests may be conducted by setting the externally applied high voltage Ve to an arbitrary level. The semiconductor integrated circuit device in FIG. 17, however, has problems which will be described in the following.
Referring to the wave form diagram of FIG. 18, generally, when a clock signal CK for controlling the operation of a semiconductor integrated circuit device transits from a high level to a low level, the state of the internal circuit changes and a current flows. Thus, the power supply current I indicates a peak. Such a peak of the power supply current I may be also observed when the clock signal CK transits from a low level to a high level. The power supply current I is provided from the external power supply via the power supply voltage converting circuit 111 to the internal integrated circuit block 113. The impedance of an output circuit (not shown) included in the power supply voltage converting circuit 111 functions as a current limiting resistor. Thus, the output circuit of the power supply voltage converting circuit 111 functions as a resistor, so that there occurs a voltage drop in the internal voltage Vi. Therefore, as shown in FIG. 18, the fluctuation of the voltage of the internal voltage Vi becomes larger compared with the voltage fluctuation of the power supply voltage Vcc. That is, the externally applied power supply voltage Vcc becomes more stable than the internal voltage Vi.
In the semiconductor integrated circuit device in FIG. 17, the amount of fluctuation of the internal voltage Vi applied to the integrated circuit block 113 at the time of normal use is different from the amount of fluctuation of the high voltage Ve applied to the integrated circuit block 113 at the time of an acceleration aging test. Therefore, there is a problem that the operating condition of the integrated circuit block 113 at the time of an acceleration aging test differs from the operating condition at the time of actual use.
Additionally, there is a possibility that the semiconductor integrated circuit device is erroneously set to an operation test mode at the time of normal use if the switch signal .phi.1 is generated for some reason. In this case, there is a problem that a high voltage is applied to the integrated circuit block 113 and the integrated circuit block 113 is destroyed.
FIG. 19 shows another example of a conventional power supply voltage converting circuit. This power supply voltage converting circuit is disclosed in Japanese Patent Laying-Open No. 63-181196.
The power supply voltage converting circuit of FIG. 19 includes a reference voltage signal generating portion 120 for generating a reference voltage Vr corresponding to the voltage level of a control signal from a control terminal 125 and a converter 130 for converting a power supply voltage Vcc to an internal voltage Vi corresponding to the reference voltage.
Transistors 121 to 124 are connected between the control terminal 125 and the node N10 within the reference voltage signal generating portion 120. Assuming that the threshold voltages of the transistors 121 to 124 are all Vt, when the voltage of the control terminal 125 becomes higher than the voltage of the node N10 by 4 Vt or above, the reference voltage Vr rises, and the internal voltage Vi supplied from the converting portion 130 also rises. When the voltage of the control terminal 125 is at or below the value, the reference voltage Vr does not change, and the internal voltage Vi supplied from the converter 130 does not change, either.
In accordance with the power supply voltage converting circuit in FIG. 19, the internal voltage Vi generated from the converter 130 may be provided both at the time of normal use and at the time of an acceleration aging test, so that there is no problem as in the semiconductor integrated circuit of FIG. 17.
In the power supply voltage converting circuit in FIG. 19, however, an internal voltage Vi at a higher level than at the time of normal use may be generated by applying a high voltage to the control terminal 125, whereas an internal voltage at a lower level than at the time of normal use cannot be generated. Accordingly, it is impossible to apply various internal voltages to the internal circuit and conduct a V bump test (voltage fluctuation test) for checking the operation margin.